In the field of semiconductor memory devices such as DRAMs (dynamic random access memories) and EBBs (embedded memories), it is well known to use an array layout in which each bitline of the array is coupled to a sense amplifier. Such a layout is shown, for example, in FIG. 1. Specifically, FIG. 1 is a schematic diagram of a prior art single-cell, folded bitline memory layout which includes memory cells 10, horizontally arranged wordlines WL1, WL2, WL3, WL4 and etc, vertically arranged bitlines BL1, BL2, BL3, BL4 and etc, transistors 12, and sense amplifiers, SA1 and SA2.
In the prior art single-cell, folded bitline memory layout shown in FIG. 1, each neighboring bitline, which forms a bitline pair, is coupled to a single sense amplifier. For example, BL1 and BL2 are both directly coupled to sense amplifier, SA1, whereas BL3 and BL4 are both directly coupled to sense amplifier SA2. Thus, each sense amplifier is capable of sensing only two bitlines in the single-cell arrangement shown in FIG. 1.
In a read operation, the bitlines are electrically connected to the sense amplifier through transistors 12 and are subjected to amplification. Through amplification, each pair of bitlines, which have been precharged to predetermined levels, are changed to different potentials. Particularly, one of each pair of bitlines is discharged to the ground potential. Since the bitlines are arranged in parallel, a stray capacitance is present between two adjacent bitlines. Therefore, a change in potential at one bitline will affect the adjacent bitline as noise through the stray capacitance.
Twin-cell, folded bitline memory arrays which generate twice as much signal as a single-cell memory array are also known. A typical twin-cell, folded bitline memory array is shown in FIG. 2. Specifically, the twin-cell memory array of FIG. 2 comprises memory cells 10, horizontally arranged wordlines WL.sub.A, WL.sub.B, and etc, and vertically arranged bitlines BL1, BL2, BL3, BL4 and etc, transistors 12 and sense amplifiers, SA1 and SA2. In the twin-cell memory layout shown in FIG. 2, WL.sub.A includes a pair of wordlines, e.g., WL1 and WL2 that are shorted together, whereas WL.sub.B denotes another pair of wordlines, e.g., WL3 and WL4, that are shorted together. In the prior art twin-cell memory structure of FIG. 2, it is required that a pair of wordlines, i.e., WL1+WL2 or WL3+WL4, be activated at the same time.
As in the case with single-cell layouts, prior art twin-cell layouts of the type illustrated in FIG. 2 exhibit bitline line-to-line coupling which causes noise problems. In view of the drawbacks with conventional single- and twin-cell, folded bitline memory layouts, there is a need for a new and improved twin-cell, folded bitline memory design in which bitline crosstalk caused by bitline line-to-line coupling has been essentially eliminated.